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| author | Clifford Wolf <clifford@clifford.at> | 2019-03-05 15:20:03 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-05 15:20:03 -0800 |
| commit | ba0da6371e6bffc3e79a0d5388a508e2b7ea775b (patch) | |
| tree | ba9b5e1f25d3e7dd51cfc7458ff88d4640fbb365 /examples/anlogic/build.tcl | |
| parent | 855b9dc60661f79252d1f49e0a93911ce7b5a9b4 (diff) | |
| parent | 32a901ddf21711e2b2fe2a0a8719ff7f69fd9489 (diff) | |
| download | yosys-ba0da6371e6bffc3e79a0d5388a508e2b7ea775b.tar.gz yosys-ba0da6371e6bffc3e79a0d5388a508e2b7ea775b.tar.bz2 yosys-ba0da6371e6bffc3e79a0d5388a508e2b7ea775b.zip | |
Merge pull request #851 from kprasadvnsi/master
Added examples/anlogic/
Diffstat (limited to 'examples/anlogic/build.tcl')
| -rw-r--r-- | examples/anlogic/build.tcl | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/examples/anlogic/build.tcl b/examples/anlogic/build.tcl new file mode 100644 index 000000000..db8c3b347 --- /dev/null +++ b/examples/anlogic/build.tcl @@ -0,0 +1,11 @@ +import_device eagle_s20.db -package BG256 +read_verilog full.v -top demo +read_adc demo.adc +optimize_rtl +map_macro +map +pack +place +route +report_area -io_info -file demo_phy.area +bitgen -bit demo.bit -version 0X00 -g ucode:00000000000000000000000000000000 |