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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-14 08:59:19 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-14 08:59:19 -0700 |
| commit | f1a8e8a480a7a88835b02abafd27c03e90de7041 (patch) | |
| tree | 49679db03662de0b029d814354f01f972179e453 /examples/anlogic/build.tcl | |
| parent | 26ecbc1aee1dca1c186ab2b51835d74f67bc3e75 (diff) | |
| parent | f0b2d8e467998876ad2cc14232d30ff7892982a3 (diff) | |
| download | yosys-f1a8e8a480a7a88835b02abafd27c03e90de7041.tar.gz yosys-f1a8e8a480a7a88835b02abafd27c03e90de7041.tar.bz2 yosys-f1a8e8a480a7a88835b02abafd27c03e90de7041.zip | |
Merge remote-tracking branch 'origin/master' into xc7srl
Diffstat (limited to 'examples/anlogic/build.tcl')
| -rw-r--r-- | examples/anlogic/build.tcl | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/examples/anlogic/build.tcl b/examples/anlogic/build.tcl new file mode 100644 index 000000000..06db525c9 --- /dev/null +++ b/examples/anlogic/build.tcl @@ -0,0 +1,11 @@ +import_device eagle_s20.db -package BG256 +read_verilog full.v -top demo +read_adc demo.adc +optimize_rtl +map_macro +map +pack +place +route +report_area -io_info -file demo_phy.area +bitgen -bit demo.bit -version 0X0000 -svf demo.svf -svf_comment_on -g ucode:00000000000000000000000000000000 |