Merge https://github.com/YosysHQ/yosys into read_aiger

1 files changed, 18 insertions, 0 deletions

diff --git a/examples/anlogic/demo.v b/examples/anlogic/demo.v
new file mode 100644
index 000000000..e17db771e
--- /dev/null
+++ b/examples/anlogic/demo.v
@@ -0,0 +1,18 @@
+module demo (
+    input wire CLK_IN,
+    output wire R_LED
+);
+    parameter time1 = 30'd12_000_000;
+    reg led_state;
+    reg [29:0] count;
+
+    always @(posedge CLK_IN)begin
+        if(count == time1)begin
+            count<= 30'd0;
+            led_state <= ~led_state;
+        end
+        else
+            count <= count + 1'b1;
+    end
+    assign R_LED = led_state;
+endmodule