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author | Benedikt Tutzer <benedikt.tutzer@tuwien.ac.at> | 2019-03-28 12:16:39 +0100 |
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committer | Benedikt Tutzer <benedikt.tutzer@tuwien.ac.at> | 2019-03-28 12:16:39 +0100 |
commit | 03d1606b42110f8eac7311ac57c7334d1f781273 (patch) | |
tree | 9fc490a93fbb75ac3e23b276a151e22ca1a3b84e /examples/anlogic/demo.v | |
parent | b9288b216dce110ad11eb0615a6a911a9fcae05b (diff) | |
parent | 32bd0f22ec93202e67395901cdc64c20df7f0da7 (diff) | |
download | yosys-03d1606b42110f8eac7311ac57c7334d1f781273.tar.gz yosys-03d1606b42110f8eac7311ac57c7334d1f781273.tar.bz2 yosys-03d1606b42110f8eac7311ac57c7334d1f781273.zip |
Merge remote-tracking branch 'origin/master' into feature/python_bindings
Diffstat (limited to 'examples/anlogic/demo.v')
-rw-r--r-- | examples/anlogic/demo.v | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/examples/anlogic/demo.v b/examples/anlogic/demo.v new file mode 100644 index 000000000..e17db771e --- /dev/null +++ b/examples/anlogic/demo.v @@ -0,0 +1,18 @@ +module demo ( + input wire CLK_IN, + output wire R_LED +); + parameter time1 = 30'd12_000_000; + reg led_state; + reg [29:0] count; + + always @(posedge CLK_IN)begin + if(count == time1)begin + count<= 30'd0; + led_state <= ~led_state; + end + else + count <= count + 1'b1; + end + assign R_LED = led_state; +endmodule |