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| author | Clifford Wolf <clifford@clifford.at> | 2019-03-07 11:34:12 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-07 11:34:12 -0800 |
| commit | df0598f455990604f51cb309831e1b95193d2dc3 (patch) | |
| tree | 4d192aee68c0b65d02402a208918fbc482a18391 /examples/anlogic/demo.v | |
| parent | 350dfd3745ec2efa92a601d3bab7712fd9bec07c (diff) | |
| parent | 7c03b0b08209c7e1b3972a05db63b23c0b1d7a5e (diff) | |
| download | yosys-df0598f455990604f51cb309831e1b95193d2dc3.tar.gz yosys-df0598f455990604f51cb309831e1b95193d2dc3.tar.bz2 yosys-df0598f455990604f51cb309831e1b95193d2dc3.zip | |
Merge pull request #856 from kprasadvnsi/master
examples/anlogic/ now also output the SVF file.
Diffstat (limited to 'examples/anlogic/demo.v')
| -rw-r--r-- | examples/anlogic/demo.v | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/examples/anlogic/demo.v b/examples/anlogic/demo.v index a7edf4e37..e17db771e 100644 --- a/examples/anlogic/demo.v +++ b/examples/anlogic/demo.v @@ -1,18 +1,18 @@ module demo ( - input wire CLK_IN, - output wire R_LED + input wire CLK_IN, + output wire R_LED ); parameter time1 = 30'd12_000_000; reg led_state; reg [29:0] count; - + always @(posedge CLK_IN)begin if(count == time1)begin - count<= 30'd0; + count<= 30'd0; led_state <= ~led_state; end else count <= count + 1'b1; end assign R_LED = led_state; -endmodule
\ No newline at end of file +endmodule |