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| author | Clifford Wolf <clifford@clifford.at> | 2019-03-07 11:34:12 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-07 11:34:12 -0800 |
| commit | df0598f455990604f51cb309831e1b95193d2dc3 (patch) | |
| tree | 4d192aee68c0b65d02402a208918fbc482a18391 /examples/anlogic/demo.ys | |
| parent | 350dfd3745ec2efa92a601d3bab7712fd9bec07c (diff) | |
| parent | 7c03b0b08209c7e1b3972a05db63b23c0b1d7a5e (diff) | |
| download | yosys-df0598f455990604f51cb309831e1b95193d2dc3.tar.gz yosys-df0598f455990604f51cb309831e1b95193d2dc3.tar.bz2 yosys-df0598f455990604f51cb309831e1b95193d2dc3.zip | |
Merge pull request #856 from kprasadvnsi/master
examples/anlogic/ now also output the SVF file.
Diffstat (limited to 'examples/anlogic/demo.ys')
| -rw-r--r-- | examples/anlogic/demo.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/examples/anlogic/demo.ys b/examples/anlogic/demo.ys index 5687bcd31..cb396cc2b 100644 --- a/examples/anlogic/demo.ys +++ b/examples/anlogic/demo.ys @@ -1,3 +1,3 @@ read_verilog demo.v synth_anlogic -top demo -write_verilog full.v
\ No newline at end of file +write_verilog full.v |