Merge pull request #7 from YosysHQ/master

Syncing with official repo

7 files changed, 57 insertions, 0 deletions

diff --git a/examples/anlogic/.gitignore b/examples/anlogic/.gitignore
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index 000000000..97c978a15
--- /dev/null
+++ b/examples/anlogic/.gitignore
@@ -0,0 +1,7 @@
+demo.bit
+demo_phy.area
+full.v
+*.log
+*.h
+*.tde
+*.svf
diff --git a/examples/anlogic/README b/examples/anlogic/README
new file mode 100644
index 000000000..35d8e9cb1
--- /dev/null
+++ b/examples/anlogic/README
@@ -0,0 +1,12 @@
+LED Blink project for Anlogic Lichee Tang board.
+
+Follow the install instructions for the Tang Dynasty IDE from given link below.
+
+https://tang.sipeed.com/en/getting-started/installing-td-ide/linux/
+
+
+set TD_HOME env variable to the full path to the TD <TD Install Directory> as follow.
+
+export TD_HOME=<TD Install Directory>
+
+then run "bash build.sh" in this directory.
diff --git a/examples/anlogic/build.sh b/examples/anlogic/build.sh
new file mode 100755
index 000000000..e0f6b4cfe
--- /dev/null
+++ b/examples/anlogic/build.sh
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+#!/bin/bash
+set -ex
+yosys demo.ys
+$TD_HOME/bin/td build.tcl
diff --git a/examples/anlogic/build.tcl b/examples/anlogic/build.tcl
new file mode 100644
index 000000000..06db525c9
--- /dev/null
+++ b/examples/anlogic/build.tcl
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+import_device eagle_s20.db -package BG256
+read_verilog full.v -top demo
+read_adc demo.adc
+optimize_rtl
+map_macro
+map
+pack
+place
+route
+report_area -io_info -file demo_phy.area
+bitgen -bit demo.bit -version 0X0000 -svf demo.svf -svf_comment_on -g ucode:00000000000000000000000000000000
diff --git a/examples/anlogic/demo.adc b/examples/anlogic/demo.adc
new file mode 100644
index 000000000..ec802502e
--- /dev/null
+++ b/examples/anlogic/demo.adc
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+set_pin_assignment {CLK_IN} { LOCATION = K14;  } ##24MHZ
+set_pin_assignment {R_LED} { LOCATION = R3;  } ##R_LED
diff --git a/examples/anlogic/demo.v b/examples/anlogic/demo.v
new file mode 100644
index 000000000..e17db771e
--- /dev/null
+++ b/examples/anlogic/demo.v
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+module demo (
+    input wire CLK_IN,
+    output wire R_LED
+);
+    parameter time1 = 30'd12_000_000;
+    reg led_state;
+    reg [29:0] count;
+
+    always @(posedge CLK_IN)begin
+        if(count == time1)begin
+            count<= 30'd0;
+            led_state <= ~led_state;
+        end
+        else
+            count <= count + 1'b1;
+    end
+    assign R_LED = led_state;
+endmodule
diff --git a/examples/anlogic/demo.ys b/examples/anlogic/demo.ys
new file mode 100644
index 000000000..cb396cc2b
--- /dev/null
+++ b/examples/anlogic/demo.ys
@@ -0,0 +1,3 @@
+read_verilog demo.v
+synth_anlogic -top demo
+write_verilog full.v