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| author | Clifford Wolf <clifford@clifford.at> | 2015-10-13 15:40:21 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-10-13 15:41:20 +0200 |
| commit | f42218682d2c7caa6caa81cb2ca48f0c3f62bb5b (patch) | |
| tree | eed220c7c84c673dec27bca4c2e96d919831f8b7 /examples/basys3/example.v | |
| parent | f13e3873212fb4338ee3dd180cb9b0cd3d134935 (diff) | |
| download | yosys-f42218682d2c7caa6caa81cb2ca48f0c3f62bb5b.tar.gz yosys-f42218682d2c7caa6caa81cb2ca48f0c3f62bb5b.tar.bz2 yosys-f42218682d2c7caa6caa81cb2ca48f0c3f62bb5b.zip | |
Added examples/ top-level directory
Diffstat (limited to 'examples/basys3/example.v')
| -rw-r--r-- | examples/basys3/example.v | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/examples/basys3/example.v b/examples/basys3/example.v new file mode 100644 index 000000000..2b01a22a8 --- /dev/null +++ b/examples/basys3/example.v @@ -0,0 +1,21 @@ +module example(CLK, LD); + input CLK; + output [15:0] LD; + + wire clock; + reg [15:0] leds; + + BUFG CLK_BUF (.I(CLK), .O(clock)); + OBUF LD_BUF[15:0] (.I(leds), .O(LD)); + + parameter COUNTBITS = 26; + reg [COUNTBITS-1:0] counter; + + always @(posedge CLK) begin + counter <= counter + 1; + if (counter[COUNTBITS-1]) + leds <= 16'h8000 >> counter[COUNTBITS-2:COUNTBITS-5]; + else + leds <= 16'h0001 << counter[COUNTBITS-2:COUNTBITS-5]; + end +endmodule |