iCE40/yosys - [no description]

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author	Miodrag Milanović <mmicko@gmail.com>	2019-10-18 10:54:04 +0200
committer	GitHub <noreply@github.com>	2019-10-18 10:54:04 +0200
commit	ab4899a2d02b994d79e4aa223eb743793b9a60b3 (patch)
tree	a78b5d92952ea9f95623bb3daf8028d2402d023b /examples/igloo2/example.pdc
parent	5ffb0053ec7d53ffc5c57e3277bfbab5d3fddb54 (diff)
parent	66fca65b58bfb944cad45da5836613726498e4b7 (diff)
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Merge pull request #1434 from YosysHQ/mmicko/anlogic

Add tests for Anlogic architecture (contd)

Diffstat (limited to 'examples/igloo2/example.pdc')

0 files changed, 0 insertions, 0 deletions

/******************************************************************************* Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. The full GNU General Public License is included in this distribution in the file called LICENSE. Contact Information: Linux NICS <linux.nics@intel.com> Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 *******************************************************************************/ /* glue for the OS independant part of e1000 * includes register access macros */ #ifndef _E1000_OSDEP_H_ #define _E1000_OSDEP_H_ #include <linux/types.h> #include <linux/pci.h> #include <linux/delay.h> #include <asm/io.h> #include <linux/interrupt.h> #include <linux/sched.h> #ifndef msec_delay #define msec_delay(x) {\ int s=jiffies+1+((x*HZ)/1000); \ while(jiffies<s); } #if 0 /******************** NOT in XEN ! *******/ #define XXXXmsec_delay(x) do { if(in_interrupt()) { \ /* Don't mdelay in interrupt context! */ \ BUG(); \ } else { \ set_current_state(TASK_UNINTERRUPTIBLE); \ schedule_timeout((x * HZ)/1000); \ } } while(0) #endif #else #error "msec already defined!" #endif #define PCI_COMMAND_REGISTER PCI_COMMAND #define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE typedef enum { FALSE = 0, TRUE = 1 } boolean_t; #define MSGOUT(S, A, B) printk(KERN_DEBUG S "\n", A, B) //#define DBG 1 #if DBG #define DEBUGOUT(S) printk(KERN_DEBUG S "\n") #define DEBUGOUT1(S, A...) printk(KERN_DEBUG S "\n", A) #else #define DEBUGOUT(S) #define DEBUGOUT1(S, A...) #endif #define DEBUGFUNC(F) DEBUGOUT(F) #define DEBUGOUT2 DEBUGOUT1 #define DEBUGOUT3 DEBUGOUT2 #define DEBUGOUT7 DEBUGOUT3 #define E1000_WRITE_REG(a, reg, value) ( \ ((a)->mac_type >= e1000_82543) ? \ (writel((value), ((a)->hw_addr + E1000_##reg))) : \ (writel((value), ((a)->hw_addr + E1000_82542_##reg)))) #define E1000_READ_REG(a, reg) ( \ ((a)->mac_type >= e1000_82543) ? \ readl((a)->hw_addr + E1000_##reg) : \ readl((a)->hw_addr + E1000_82542_##reg)) #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \ ((a)->mac_type >= e1000_82543) ? \ writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2))) : \ writel((value), ((a)->hw_addr + E1000_82542_##reg + ((offset) << 2)))) #define E1000_READ_REG_ARRAY(a, reg, offset) ( \ ((a)->mac_type >= e1000_82543) ? \ readl((a)->hw_addr + E1000_##reg + ((offset) << 2)) : \ readl((a)->hw_addr + E1000_82542_##reg + ((offset) << 2))) #define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, STATUS) #endif /* _E1000_OSDEP_H_ */


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