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authorEddie Hung <eddieh@ece.ubc.ca>2019-03-19 08:52:31 -0700
committerEddie Hung <eddieh@ece.ubc.ca>2019-03-19 08:52:31 -0700
commit02e8dc7ad2e13a43a310d311302c6db8168e6c11 (patch)
treeaf43bf9735fe47b09dbd8807c63fe451eb82aaba /examples/igloo2/example.sdc
parent3e89cf68bdc4e9eeb55bd9450121f421bcdc554a (diff)
parent61f37706f93042c2d1f093dd9bfa717390911eb3 (diff)
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Merge https://github.com/YosysHQ/yosys into read_aiger
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diff --git a/examples/igloo2/example.sdc b/examples/igloo2/example.sdc
index c6ff94161..f8b487316 100644
--- a/examples/igloo2/example.sdc
+++ b/examples/igloo2/example.sdc
@@ -1 +1,2 @@
# Add timing constraints here
+create_clock -period 10.000 -waveform {0.000 5.000} [get_ports {clk}]