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author | Clifford Wolf <clifford@clifford.at> | 2019-02-17 12:10:19 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2019-02-17 12:10:19 +0100 |
commit | c06c062469a6f5ea16116a5ed3bc4a45b6e818a2 (patch) | |
tree | ea54f3510f2e85771422718385028b0864696cba /examples/igloo2/example.v | |
parent | 8ddec5d882c6834cb6b3415e05a2a88d416cabff (diff) | |
parent | e45f62b0c56717a23099425f078d1e56212aa632 (diff) | |
download | yosys-c06c062469a6f5ea16116a5ed3bc4a45b6e818a2.tar.gz yosys-c06c062469a6f5ea16116a5ed3bc4a45b6e818a2.tar.bz2 yosys-c06c062469a6f5ea16116a5ed3bc4a45b6e818a2.zip |
Merge branch 'master' of github.com:YosysHQ/yosys into pmgen
Diffstat (limited to 'examples/igloo2/example.v')
-rw-r--r-- | examples/igloo2/example.v | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/examples/igloo2/example.v b/examples/igloo2/example.v index 3eb7007c5..1a1967d5a 100644 --- a/examples/igloo2/example.v +++ b/examples/igloo2/example.v @@ -1,5 +1,6 @@ -module top ( +module example ( input clk, + input EN, output LED1, output LED2, output LED3, @@ -14,7 +15,7 @@ module top ( reg [BITS-1:0] outcnt; always @(posedge clk) begin - counter <= counter + 1; + counter <= counter + EN; outcnt <= counter >> LOG2DELAY; end |