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author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-19 08:52:31 -0700 |
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committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-19 08:52:31 -0700 |
commit | 02e8dc7ad2e13a43a310d311302c6db8168e6c11 (patch) | |
tree | af43bf9735fe47b09dbd8807c63fe451eb82aaba /examples/igloo2/libero.tcl | |
parent | 3e89cf68bdc4e9eeb55bd9450121f421bcdc554a (diff) | |
parent | 61f37706f93042c2d1f093dd9bfa717390911eb3 (diff) | |
download | yosys-02e8dc7ad2e13a43a310d311302c6db8168e6c11.tar.gz yosys-02e8dc7ad2e13a43a310d311302c6db8168e6c11.tar.bz2 yosys-02e8dc7ad2e13a43a310d311302c6db8168e6c11.zip |
Merge https://github.com/YosysHQ/yosys into read_aiger
Diffstat (limited to 'examples/igloo2/libero.tcl')
-rw-r--r-- | examples/igloo2/libero.tcl | 18 |
1 files changed, 11 insertions, 7 deletions
diff --git a/examples/igloo2/libero.tcl b/examples/igloo2/libero.tcl index 1f3476316..abc94e479 100644 --- a/examples/igloo2/libero.tcl +++ b/examples/igloo2/libero.tcl @@ -8,13 +8,14 @@ new_project \ -block_mode 0 \ -hdl "VERILOG" \ -family IGLOO2 \ - -die PA4MGL500 \ - -package tq144 \ + -die PA4MGL2500 \ + -package vf256 \ -speed -1 import_files -hdl_source {netlist.vm} import_files -sdc {example.sdc} import_files -io_pdc {example.pdc} +build_design_hierarchy set_option -synth 0 organize_tool_files -tool PLACEROUTE \ @@ -32,22 +33,25 @@ configure_tool -name PLACEROUTE \ -params EFFORT_LEVEL:false \ -params REPAIR_MIN_DELAY:false +puts "" puts "**> COMPILE" run_tool -name {COMPILE} puts "<** COMPILE" +puts "" puts "**> PLACEROUTE" run_tool -name {PLACEROUTE} puts "<** PLACEROUTE" +puts "" puts "**> VERIFYTIMING" run_tool -name {VERIFYTIMING} puts "<** VERIFYTIMING" -save_project - -# puts "**> export_bitstream" -# export_bitstream_file -trusted_facility_file 1 -trusted_facility_file_components {FABRIC} -# puts "<** export_bitstream" +puts "" +puts "**> BITSTREAM" +export_bitstream_file -trusted_facility_file 1 -trusted_facility_file_components {FABRIC} +puts "<** BITSTREAM" +puts "" exit 0 |