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author | dh73 <dh73_fpga@qq.com> | 2017-04-05 23:01:29 -0500 |
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committer | dh73 <dh73_fpga@qq.com> | 2017-04-05 23:01:29 -0500 |
commit | c27dcc1e47fa00cd415893c9d3f637a5d5865988 (patch) | |
tree | f474149e35f09f18cc6ff701ec03c667bd76477c /examples/intel/MAX10/run_max10 | |
parent | fcb274a5644016c4090cdfbfbd795f311a7e58f5 (diff) | |
download | yosys-c27dcc1e47fa00cd415893c9d3f637a5d5865988.tar.gz yosys-c27dcc1e47fa00cd415893c9d3f637a5d5865988.tar.bz2 yosys-c27dcc1e47fa00cd415893c9d3f637a5d5865988.zip |
Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs
Diffstat (limited to 'examples/intel/MAX10/run_max10')
-rw-r--r-- | examples/intel/MAX10/run_max10 | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/examples/intel/MAX10/run_max10 b/examples/intel/MAX10/run_max10 new file mode 100644 index 000000000..ef7649afb --- /dev/null +++ b/examples/intel/MAX10/run_max10 @@ -0,0 +1 @@ +yosys -p "synth_intel -family max10 -top top -vout top.vqm" top.v sevenseg.v |