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| author | dh73 <dh73_fpga@qq.com> | 2017-04-05 23:01:29 -0500 |
|---|---|---|
| committer | dh73 <dh73_fpga@qq.com> | 2017-04-05 23:01:29 -0500 |
| commit | c27dcc1e47fa00cd415893c9d3f637a5d5865988 (patch) | |
| tree | f474149e35f09f18cc6ff701ec03c667bd76477c /examples/intel/MAX10/top.v | |
| parent | fcb274a5644016c4090cdfbfbd795f311a7e58f5 (diff) | |
| download | yosys-c27dcc1e47fa00cd415893c9d3f637a5d5865988.tar.gz yosys-c27dcc1e47fa00cd415893c9d3f637a5d5865988.tar.bz2 yosys-c27dcc1e47fa00cd415893c9d3f637a5d5865988.zip | |
Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs
Diffstat (limited to 'examples/intel/MAX10/top.v')
| -rw-r--r-- | examples/intel/MAX10/top.v | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/examples/intel/MAX10/top.v b/examples/intel/MAX10/top.v new file mode 100644 index 000000000..75c778feb --- /dev/null +++ b/examples/intel/MAX10/top.v @@ -0,0 +1,15 @@ +`default_nettype none +module top ( output wire [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7, + input wire [15:0] SW ); + + + sevenseg UUD0 (.HEX0(HEX0), .SW(4'h7)); + sevenseg UUD1 (.HEX0(HEX1), .SW(4'h1)); + sevenseg UUD2 (.HEX0(HEX2), .SW(4'h0)); + sevenseg UUD3 (.HEX0(HEX3), .SW(4'h2)); + sevenseg UUD4 (.HEX0(HEX4), .SW(SW[3:0])); + sevenseg UUD5 (.HEX0(HEX5), .SW(SW[7:4])); + sevenseg UUD6 (.HEX0(HEX6), .SW(SW[11:8])); + sevenseg UUD7 (.HEX0(HEX7), .SW(SW[15:12])); + +endmodule |