Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs

7 files changed, 89 insertions, 0 deletions

diff --git a/examples/intel/asicworld_lfsr/README b/examples/intel/asicworld_lfsr/README
new file mode 100644
index 000000000..ba365fabf
--- /dev/null
+++ b/examples/intel/asicworld_lfsr/README
@@ -0,0 +1,6 @@
+Source of the files:
+http://www.asic-world.com/examples/verilog/lfsr.html
+
+Run first: runme_presynth
+Generate output netlist with run_max10 or run_cycloneiv
+Then, check with: runme_postsynth
diff --git a/examples/intel/asicworld_lfsr/lfsr_updown.v b/examples/intel/asicworld_lfsr/lfsr_updown.v
new file mode 100644
index 000000000..43db1606a
--- /dev/null
+++ b/examples/intel/asicworld_lfsr/lfsr_updown.v
@@ -0,0 +1,35 @@
+`default_nettype none
+module lfsr_updown (
+clk       ,   // Clock input
+reset     ,   // Reset input
+enable    ,   // Enable input
+up_down   ,   // Up Down input
+count     ,   // Count output
+overflow      // Overflow output
+);
+
+ input clk;
+ input reset;
+ input enable; 
+ input up_down;
+
+ output [7 : 0] count;
+ output overflow;
+
+ reg [7 : 0] count;
+
+ assign overflow = (up_down) ? (count == {{7{1'b0}}, 1'b1}) : 
+                               (count == {1'b1, {7{1'b0}}}) ;
+
+ always @(posedge clk)
+ if (reset) 
+    count <= {7{1'b0}};
+ else if (enable) begin
+    if (up_down) begin
+      count <= {~(^(count & 8'b01100011)),count[7:1]};
+    end else begin
+      count <= {count[5:0],~(^(count &  8'b10110001))};
+    end
+ end
+
+endmodule
diff --git a/examples/intel/asicworld_lfsr/lfsr_updown_tb.v b/examples/intel/asicworld_lfsr/lfsr_updown_tb.v
new file mode 100644
index 000000000..db29e60f1
--- /dev/null
+++ b/examples/intel/asicworld_lfsr/lfsr_updown_tb.v
@@ -0,0 +1,34 @@
+module tb();
+ reg clk;
+ reg reset;
+ reg enable;
+ reg up_down;
+
+ wire [7 : 0] count;
+ wire overflow;
+
+initial begin
+  $monitor("rst %b en %b updown %b cnt %b overflow %b",
+     reset,enable,up_down,count, overflow);
+  clk = 0;
+  reset = 1;
+  enable = 0;
+  up_down = 0;
+  #10 reset = 0;
+  #1 enable = 1;
+  #20 up_down = 1;
+  #30 $finish;
+end
+
+always #1 clk = ~clk;
+
+lfsr_updown U(
+.clk      ( clk      ),
+.reset    ( reset    ),
+.enable   ( enable   ),
+.up_down  ( up_down  ),
+.count    ( count    ),
+.overflow ( overflow )
+);
+
+endmodule 
diff --git a/examples/intel/asicworld_lfsr/run_cycloneiv b/examples/intel/asicworld_lfsr/run_cycloneiv
new file mode 100755
index 000000000..cb7f5c9b1
--- /dev/null
+++ b/examples/intel/asicworld_lfsr/run_cycloneiv
@@ -0,0 +1,2 @@
+#!/bin/env bash
+yosys -p "synth_intel -family cycloneiv -top lfsr_updown -vout top.vqm" lfsr_updown.v
diff --git a/examples/intel/asicworld_lfsr/run_max10 b/examples/intel/asicworld_lfsr/run_max10
new file mode 100755
index 000000000..6bb812c16
--- /dev/null
+++ b/examples/intel/asicworld_lfsr/run_max10
@@ -0,0 +1,2 @@
+#!/bin/env bash
+yosys -p "synth_intel -family max10 -top lfsr_updown -vout top.vqm" lfsr_updown.v
diff --git a/examples/intel/asicworld_lfsr/runme_postsynth b/examples/intel/asicworld_lfsr/runme_postsynth
new file mode 100755
index 000000000..c3b26b034
--- /dev/null
+++ b/examples/intel/asicworld_lfsr/runme_postsynth
@@ -0,0 +1,5 @@
+#!/bin/bash
+
+iverilog -D POST_IMPL -o verif_post -s tb lfsr_updown_tb.v top.vqm $(yosys-config --datdir/altera_intel/max10/cells_comb_max10.v)
+vvp -N verif_post
+
diff --git a/examples/intel/asicworld_lfsr/runme_presynth b/examples/intel/asicworld_lfsr/runme_presynth
new file mode 100755
index 000000000..51118bb4b
--- /dev/null
+++ b/examples/intel/asicworld_lfsr/runme_presynth
@@ -0,0 +1,5 @@
+#!/bin/bash
+
+iverilog -o presynth lfsr_updown_tb.v lfsr_updown.v &&\
+
+vvp -N presynth
\ No newline at end of file