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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-16 16:51:22 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-16 16:51:22 -0700 |
| commit | 24c934f1af3859fe64ff4fb87a2a3de97695cde4 (patch) | |
| tree | 131c64cee5a0cf09adc68b32f25e06a9da668ad0 /examples/mimas2/example.v | |
| parent | 1c9f3fadb9f60653fc9d1d7d72ba22033e077468 (diff) | |
| parent | 5abe133323b2a6a46959f796c4730b2d70cdea26 (diff) | |
| download | yosys-24c934f1af3859fe64ff4fb87a2a3de97695cde4.tar.gz yosys-24c934f1af3859fe64ff4fb87a2a3de97695cde4.tar.bz2 yosys-24c934f1af3859fe64ff4fb87a2a3de97695cde4.zip | |
Merge branch 'eddie/abc9_refactor' into xaig_dff
Diffstat (limited to 'examples/mimas2/example.v')
| -rw-r--r-- | examples/mimas2/example.v | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/examples/mimas2/example.v b/examples/mimas2/example.v new file mode 100644 index 000000000..2a9117393 --- /dev/null +++ b/examples/mimas2/example.v @@ -0,0 +1,14 @@ +module example( + input wire CLK, + output wire [7:0] LED +); + +reg [27:0] ctr; +initial ctr = 0; + +always @(posedge CLK) + ctr <= ctr + 1; + +assign LED = ctr[27:20]; + +endmodule |