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author | Eddie Hung <eddie@fpgeh.com> | 2019-08-06 14:50:00 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-06 14:50:00 -0700 |
commit | 26cb3e7afc603b5aa703434c2cdfad444a4d4db0 (patch) | |
tree | cb346623885c4bc1e98affc623084f58b0a87ce2 /examples/mimas2/example.v | |
parent | 09beeee38a5af767f70d24e86c976e43b1b27547 (diff) | |
parent | 8110fb9266e685aaea48359a5aebc4e5ac865240 (diff) | |
download | yosys-26cb3e7afc603b5aa703434c2cdfad444a4d4db0.tar.gz yosys-26cb3e7afc603b5aa703434c2cdfad444a4d4db0.tar.bz2 yosys-26cb3e7afc603b5aa703434c2cdfad444a4d4db0.zip |
Merge remote-tracking branch 'origin/master' into eddie/wreduce_add
Diffstat (limited to 'examples/mimas2/example.v')
-rw-r--r-- | examples/mimas2/example.v | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/examples/mimas2/example.v b/examples/mimas2/example.v new file mode 100644 index 000000000..2a9117393 --- /dev/null +++ b/examples/mimas2/example.v @@ -0,0 +1,14 @@ +module example( + input wire CLK, + output wire [7:0] LED +); + +reg [27:0] ctr; +initial ctr = 0; + +always @(posedge CLK) + ctr <= ctr + 1; + +assign LED = ctr[27:20]; + +endmodule |