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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-01 12:02:16 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-01 12:02:16 -0700 |
| commit | ed303b07b770c6aa4bc69f04bc517ce4701988ed (patch) | |
| tree | 47eba7043cf616be11d30f8302a7036e89392965 /examples/mimas2/example.v | |
| parent | 7e86c8bcfb10f6a819273ad8bd10fa461987f2f1 (diff) | |
| parent | e8a2d10982cd8f6ba3b0e66fbd922b051073f0cf (diff) | |
| download | yosys-ed303b07b770c6aa4bc69f04bc517ce4701988ed.tar.gz yosys-ed303b07b770c6aa4bc69f04bc517ce4701988ed.tar.bz2 yosys-ed303b07b770c6aa4bc69f04bc517ce4701988ed.zip | |
Merge remote-tracking branch 'origin/master' into xc7dsp
Diffstat (limited to 'examples/mimas2/example.v')
| -rw-r--r-- | examples/mimas2/example.v | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/examples/mimas2/example.v b/examples/mimas2/example.v new file mode 100644 index 000000000..2a9117393 --- /dev/null +++ b/examples/mimas2/example.v @@ -0,0 +1,14 @@ +module example( + input wire CLK, + output wire [7:0] LED +); + +reg [27:0] ctr; +initial ctr = 0; + +always @(posedge CLK) + ctr <= ctr + 1; + +assign LED = ctr[27:20]; + +endmodule |