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authorEddie Hung <eddie@fpgeh.com>2019-07-24 10:51:03 -0700
committerGitHub <noreply@github.com>2019-07-24 10:51:03 -0700
commitd6a289d3e3a09d1f11ec1588a4b4e9d6846517e8 (patch)
tree0303e68642bb955029a71788beb1efabc7437c7e /examples/mimas2/run_yosys.ys
parenta66f17b6a78af8f6989235f0c72d5548b0560a58 (diff)
parent173c97589471b5f4312acac4e396a250ee7158c1 (diff)
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Merge pull request #1222 from koriakin/s6-example
Add a simple example for Spartan 6
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+read_verilog example.v
+synth_xilinx -top example -family xc6s
+iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I
+write_edif -pvector bra example.edif