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authorClifford Wolf <clifford@clifford.at>2017-05-23 18:38:20 +0200
committerClifford Wolf <clifford@clifford.at>2017-05-23 18:38:20 +0200
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Add examples/osu035
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+module top (input clk, input [7:0] a, b, output reg [15:0] c);
+ always @(posedge clk) c <= a * b;
+endmodule