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| author | Clifford Wolf <clifford@clifford.at> | 2016-07-30 12:50:39 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-07-30 12:50:39 +0200 |
| commit | 21e1bac0846e01fb58ae1fd42215b92f245ae18d (patch) | |
| tree | 43c1c9fff3a78d7221c6e5dfbfebe820b311afa1 /examples | |
| parent | 5fe13a16eaaee4ac53523b5325cb9d92b5a1150d (diff) | |
| parent | da56a5bbc60e58c305227105b68654264738c241 (diff) | |
| download | yosys-21e1bac0846e01fb58ae1fd42215b92f245ae18d.tar.gz yosys-21e1bac0846e01fb58ae1fd42215b92f245ae18d.tar.bz2 yosys-21e1bac0846e01fb58ae1fd42215b92f245ae18d.zip | |
Merge branch 'master' of github.com:cliffordwolf/yosys
Diffstat (limited to 'examples')
| -rw-r--r-- | examples/smtbmc/demo1.v | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/examples/smtbmc/demo1.v b/examples/smtbmc/demo1.v index 2e628b7da..b1e505bdd 100644 --- a/examples/smtbmc/demo1.v +++ b/examples/smtbmc/demo1.v @@ -1,5 +1,5 @@ module demo1(input clk, input addtwo, output iseven); - reg [3:0] cnt = 0; + reg [3:0] cnt; wire [3:0] next_cnt; inc inc_inst (addtwo, iseven, cnt, next_cnt); @@ -8,6 +8,7 @@ module demo1(input clk, input addtwo, output iseven); cnt = (iseven ? cnt == 10 : cnt == 11) ? 0 : next_cnt; assert property (cnt != 15); + initial assume (!cnt[3] && !cnt[0]); // initial predict ((iseven && addtwo) || cnt == 9); endmodule |