Merge branch 'eddie/abc9_refactor' of github.com:YosysHQ/yosys into eddie/abc9_refactor

1 files changed, 4 insertions, 8 deletions

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index bded2bfee..b4304a581 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -756,12 +756,6 @@ void AigerReader::post_process()
 	}
 
 	for (uint32_t i = 0; i < flopNum; i++) {
-		log_assert(co_count < outputs.size());
-		Wire *wire = outputs[co_count++];
-		log_assert(wire);
-		log_assert(wire->port_output);
-		wire->port_output = false;
-
 		RTLIL::Wire *d = outputs[outputs.size() - flopNum + i];
 		log_assert(d);
 		log_assert(d->port_output);
@@ -803,6 +797,7 @@ void AigerReader::post_process()
 						wire->port_input = false;
 						module->connect(wire, existing);
 					}
+					log_debug(" -> %s\n", log_id(escaped_s));
 				}
 				else if (index > 0) {
 					std::string indexed_name = stringf("%s[%d]", escaped_s.c_str(), index);
@@ -816,8 +811,8 @@ void AigerReader::post_process()
 						module->connect(wire, existing);
 						wire->port_input = false;
 					}
+					log_debug(" -> %s\n", log_id(indexed_name));
 				}
-				log_debug(" -> %s\n", log_id(wire));
 			}
 			else if (type == "output") {
 				log_assert(static_cast<unsigned>(variable + co_count) < outputs.size());
@@ -839,6 +834,7 @@ void AigerReader::post_process()
 						module->connect(wire, existing);
 						wire = existing;
 					}
+					log_debug(" -> %s\n", log_id(escaped_s));
 				}
 				else if (index > 0) {
 					std::string indexed_name = stringf("%s[%d]", escaped_s.c_str(), index);
@@ -852,8 +848,8 @@ void AigerReader::post_process()
 						module->connect(wire, existing);
 						wire->port_output = false;
 					}
+					log_debug(" -> %s\n", log_id(indexed_name));
 				}
-				log_debug(" -> %s\n", log_id(wire));
 				int init;
 				mf >> init;
 				if (init < 2)