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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-16 13:45:51 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-16 13:45:51 -0800 |
| commit | 1a25ec4baa705c6e809f6e8616d54da14f51bc22 (patch) | |
| tree | db024140fdd20dc3f7553d68abed9a8dee5e3f61 /frontends/aiger/aigerparse.cc | |
| parent | e7c7ab8fc06b3accc7f6d98313ec09e54a605124 (diff) | |
| download | yosys-1a25ec4baa705c6e809f6e8616d54da14f51bc22.tar.gz yosys-1a25ec4baa705c6e809f6e8616d54da14f51bc22.tar.bz2 yosys-1a25ec4baa705c6e809f6e8616d54da14f51bc22.zip | |
read_aiger to disable log_debug
Diffstat (limited to 'frontends/aiger/aigerparse.cc')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 8493264f5..84fe74f56 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -33,6 +33,7 @@ YOSYS_NAMESPACE_BEGIN #define log_debug log +#define log_debug(...) ; AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports) : design(design), f(f), clk_name(clk_name), map_filename(map_filename), wideports(wideports) @@ -627,8 +628,8 @@ void AigerReader::parse_aiger_binary() log_debug("%d is an output\n", l1); wire = createWireIfNotExists(module, l1); } - wire->port_output = true; log_assert(!wire->port_input); + wire->port_output = true; outputs.push_back(wire); } std::getline(f, line); // Ignore up to start of next line |