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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-08 10:53:38 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-10-08 10:53:38 -0700 |
| commit | 9fd2ddb14c0f7c40f6ed01a5db61cb6b327d877f (patch) | |
| tree | 526027efe405ddd8741558d150a341478d269d1f /frontends/aiger/aigerparse.cc | |
| parent | 472b5d33a624c2e414ce733c1cda0b97bce24094 (diff) | |
| parent | a5ac33f230b5dd20273f6636e5b573ef0478b8f9 (diff) | |
| download | yosys-9fd2ddb14c0f7c40f6ed01a5db61cb6b327d877f.tar.gz yosys-9fd2ddb14c0f7c40f6ed01a5db61cb6b327d877f.tar.bz2 yosys-9fd2ddb14c0f7c40f6ed01a5db61cb6b327d877f.zip | |
Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9
Rename abc_* names/attributes to more precisely be abc9_*
Diffstat (limited to 'frontends/aiger/aigerparse.cc')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 5a1da4db1..cf060193d 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -740,22 +740,22 @@ void AigerReader::post_process() log_assert(box_module); if (seen_boxes.insert(cell->type).second) { - auto it = box_module->attributes.find("\\abc_carry"); + auto it = box_module->attributes.find("\\abc9_carry"); if (it != box_module->attributes.end()) { RTLIL::Wire *carry_in = nullptr, *carry_out = nullptr; auto carry_in_out = it->second.decode_string(); auto pos = carry_in_out.find(','); if (pos == std::string::npos) - log_error("'abc_carry' attribute on module '%s' does not contain ','.\n", log_id(cell->type)); + log_error("'abc9_carry' attribute on module '%s' does not contain ','.\n", log_id(cell->type)); auto carry_in_name = RTLIL::escape_id(carry_in_out.substr(0, pos)); carry_in = box_module->wire(carry_in_name); if (!carry_in || !carry_in->port_input) - log_error("'abc_carry' on module '%s' contains '%s' which does not exist or is not an input port.\n", log_id(cell->type), carry_in_name.c_str()); + log_error("'abc9_carry' on module '%s' contains '%s' which does not exist or is not an input port.\n", log_id(cell->type), carry_in_name.c_str()); auto carry_out_name = RTLIL::escape_id(carry_in_out.substr(pos+1)); carry_out = box_module->wire(carry_out_name); if (!carry_out || !carry_out->port_output) - log_error("'abc_carry' on module '%s' contains '%s' which does not exist or is not an output port.\n", log_id(cell->type), carry_out_name.c_str()); + log_error("'abc9_carry' on module '%s' contains '%s' which does not exist or is not an output port.\n", log_id(cell->type), carry_out_name.c_str()); auto &ports = box_module->ports; for (auto jt = ports.begin(); jt != ports.end(); ) { |