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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-13 17:19:30 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-13 17:19:30 -0800 |
| commit | c7ef3863f3181c0298d166562858dec4a7faa759 (patch) | |
| tree | 0d61064ade939254e3fde2009577d1e1e2cc7c73 /frontends/aiger/aigerparse.cc | |
| parent | 396da54b5297e644087c63cd7bfb244e7ae81e3a (diff) | |
| download | yosys-c7ef3863f3181c0298d166562858dec4a7faa759.tar.gz yosys-c7ef3863f3181c0298d166562858dec4a7faa759.tar.bz2 yosys-c7ef3863f3181c0298d166562858dec4a7faa759.zip | |
Leave FIXME for clean
Diffstat (limited to 'frontends/aiger/aigerparse.cc')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 931d2fd36..92700bca7 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -317,10 +317,8 @@ void AigerReader::parse_xaiger() wire->port_output = other_wire->port_output; other_wire->port_input = false; other_wire->port_output = false; - if (wire->port_input) { - log_debug("assign %s = %s [%d];\n", other_wire->name.c_str(), wire->name.c_str(), i); + if (wire->port_input) module->connect(other_wire, SigSpec(wire, i)); - } else module->connect(SigSpec(wire, i), other_wire); } @@ -329,6 +327,8 @@ void AigerReader::parse_xaiger() module->fixup_ports(); design->add(module); + // FIXME: 'clean'-ing causes assertion fail in abc9.cc, and checks to fail... + //Pass::call(design, "clean"); } void AigerReader::parse_aiger_ascii() |