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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-23 13:42:35 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-23 13:42:35 -0700 |
| commit | d9c915042a610672e313f976cdbcbf9a814c380d (patch) | |
| tree | edb927dc53b4678878b1a04ba3614c66cd6feaf6 /frontends/aiger/aigerparse.cc | |
| parent | 91c3afcab723d85d3c6931561cb13ad7b70e7e5c (diff) | |
| download | yosys-d9c915042a610672e313f976cdbcbf9a814c380d.tar.gz yosys-d9c915042a610672e313f976cdbcbf9a814c380d.tar.bz2 yosys-d9c915042a610672e313f976cdbcbf9a814c380d.zip | |
Move clean from aigerparse to abc9
Diffstat (limited to 'frontends/aiger/aigerparse.cc')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index b9ab6fc09..904a1079d 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -598,8 +598,6 @@ next_line: module->fixup_ports(); design->add(module); - Pass::call(design, "clean"); - for (auto cell : module->cells().to_vector()) { if (cell->type != "$lut") continue; auto y_port = cell->getPort("\\Y").as_bit(); |