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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-28 08:45:10 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-28 08:45:10 -0700 |
| commit | f745727de5af085412b2e5f8161aa1018cc5e276 (patch) | |
| tree | 6b23c0cce80c868a914e89c69f7cd66c29cace11 /frontends/aiger/aigerparse.cc | |
| parent | 4a76b425cc0588ef5a8e46c06eecbfab869a35d9 (diff) | |
| download | yosys-f745727de5af085412b2e5f8161aa1018cc5e276.tar.gz yosys-f745727de5af085412b2e5f8161aa1018cc5e276.tar.bz2 yosys-f745727de5af085412b2e5f8161aa1018cc5e276.zip | |
read_aiger to only clean own design
Diffstat (limited to 'frontends/aiger/aigerparse.cc')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index e8a355671..8d7588f88 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -722,8 +722,14 @@ void AigerReader::post_process() module->fixup_ports(); design->add(module); + design->selection_stack.emplace_back(false); + RTLIL::Selection& sel = design->selection_stack.back(); + sel.select(module); + Pass::call(design, "clean"); + design->selection_stack.pop_back(); + for (auto cell : module->cells().to_vector()) { if (cell->type != "$lut") continue; auto y_port = cell->getPort("\\Y").as_bit(); |