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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-22 14:21:25 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-22 14:21:25 -0800 |
| commit | 73526a6f103c927dd0d1504281659a87e7943688 (patch) | |
| tree | 9e31df52a84af2d20ca5d4bb7b4f436557d7b1f9 /frontends/aiger/aigerparse.h | |
| parent | 8eb5bb258c161d4d6cd5b00737dfc7622fdc7f69 (diff) | |
| download | yosys-73526a6f103c927dd0d1504281659a87e7943688.tar.gz yosys-73526a6f103c927dd0d1504281659a87e7943688.tar.bz2 yosys-73526a6f103c927dd0d1504281659a87e7943688.zip | |
read_aiger: also parse abc9_mergeability
Diffstat (limited to 'frontends/aiger/aigerparse.h')
| -rw-r--r-- | frontends/aiger/aigerparse.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/aiger/aigerparse.h b/frontends/aiger/aigerparse.h index 722f1e472..46ac81212 100644 --- a/frontends/aiger/aigerparse.h +++ b/frontends/aiger/aigerparse.h @@ -45,6 +45,7 @@ struct AigerReader std::vector<RTLIL::Wire*> outputs; std::vector<RTLIL::Wire*> bad_properties; std::vector<RTLIL::Cell*> boxes; + std::vector<int> mergeability; AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports); void parse_aiger(); |