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author | Eddie Hung <eddie@fpgeh.com> | 2020-01-14 11:40:40 -0800 |
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committer | GitHub <noreply@github.com> | 2020-01-14 11:40:40 -0800 |
commit | 9fa0e03cc90548d0817346d0fcd72473b7d489ae (patch) | |
tree | 7908b1fb233a8ec4c6b99a632c768b1f93dc3387 /frontends/aiger/aigerparse.h | |
parent | 9fbeb57bbdb98265b541d7a62213e83de63c8a1a (diff) | |
parent | f63f76c372e8003f60565ee109d38ae1797d7e89 (diff) | |
download | yosys-9fa0e03cc90548d0817346d0fcd72473b7d489ae.tar.gz yosys-9fa0e03cc90548d0817346d0fcd72473b7d489ae.tar.bz2 yosys-9fa0e03cc90548d0817346d0fcd72473b7d489ae.zip |
Merge pull request #1632 from YosysHQ/eddie/fix1630
read_aiger: uniquify wires with $aiger<autoidx> prefix
Diffstat (limited to 'frontends/aiger/aigerparse.h')
-rw-r--r-- | frontends/aiger/aigerparse.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/frontends/aiger/aigerparse.h b/frontends/aiger/aigerparse.h index de3c3efbc..722f1e472 100644 --- a/frontends/aiger/aigerparse.h +++ b/frontends/aiger/aigerparse.h @@ -33,6 +33,7 @@ struct AigerReader RTLIL::Module *module; std::string map_filename; bool wideports; + const int aiger_autoidx; unsigned M, I, L, O, A; unsigned B, C, J, F; // Optional in AIGER 1.9 @@ -51,6 +52,8 @@ struct AigerReader void parse_aiger_ascii(); void parse_aiger_binary(); void post_process(); + + RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned literal); }; YOSYS_NAMESPACE_END |