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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-28 10:37:16 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-28 10:37:16 -0800 |
| commit | 6d27d4372730cb94306a4f314482459f9d527d7c (patch) | |
| tree | 1d1ed19e628d8bb17c48c2b100d525d7bc05672e /frontends/aiger | |
| parent | e18aeda7ed3b3dbf4700e25c2bc745c93541b3b8 (diff) | |
| download | yosys-6d27d4372730cb94306a4f314482459f9d527d7c.tar.gz yosys-6d27d4372730cb94306a4f314482459f9d527d7c.tar.bz2 yosys-6d27d4372730cb94306a4f314482459f9d527d7c.zip | |
Add and use SigSpec::reverse()
Diffstat (limited to 'frontends/aiger')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index f92a11c6d..a42569301 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -410,7 +410,7 @@ void AigerReader::parse_xaiger() RTLIL::Wire *output_sig = module->wire(stringf("$aiger%d$%d", aiger_autoidx, rootNodeID)); log_assert(output_sig); uint32_t nodeID; - std::vector<SigBit> input_bits; + RTLIL::SigSpec input_sig; for (unsigned j = 0; j < cutLeavesM; ++j) { nodeID = parse_xaiger_literal(f); log_debug2("\t%u\n", nodeID); @@ -420,10 +420,10 @@ void AigerReader::parse_xaiger() } RTLIL::Wire *wire = module->wire(stringf("$aiger%d$%d", aiger_autoidx, nodeID)); log_assert(wire); - input_bits.push_back(wire); + input_sig.append(wire); } // Reverse input order as fastest input is returned first - RTLIL::SigSpec input_sig(std::vector<SigBit>(input_bits.rbegin(), input_bits.rend())); + input_sig.reverse(); // TODO: Compute LUT mask from AIG in less than O(2 ** input_sig.size()) ce.clear(); ce.compute_deps(output_sig, input_sig.to_sigbit_pool()); |