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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-10 23:24:21 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-10 23:24:21 +0100 |
| commit | 378cc509cd7dcb9db9f1e1b4023ab686955bc9f6 (patch) | |
| tree | c2779ef932231c89e6467b6d221e8abc36c11a38 /frontends/ast/ast.cc | |
| parent | 223892ac286b1dd0d09bf2449cd8953b1029ae68 (diff) | |
| download | yosys-378cc509cd7dcb9db9f1e1b4023ab686955bc9f6.tar.gz yosys-378cc509cd7dcb9db9f1e1b4023ab686955bc9f6.tar.bz2 yosys-378cc509cd7dcb9db9f1e1b4023ab686955bc9f6.zip | |
Call internal checker more often
Diffstat (limited to 'frontends/ast/ast.cc')
| -rw-r--r-- | frontends/ast/ast.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index bf7d0c38c..115a39333 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -856,6 +856,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map<RTLIL::IdStrin if (design->modules.count(modname) == 0) { new_ast->str = modname; design->modules[modname] = process_module(new_ast); + design->modules[modname]->check(); } else { log("Found cached RTLIL representation for module `%s'.\n", modname.c_str()); } |