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| author | Clifford Wolf <clifford@clifford.at> | 2014-06-16 15:05:37 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-06-16 15:05:37 +0200 |
| commit | 82bbd2f0772e62555eb669eb64883d75de4ca29a (patch) | |
| tree | fb974ae6cf552f19ee6fe1cbf563373de5c4fb95 /frontends/ast/ast.cc | |
| parent | 0c4c79c4c6f8a433ef4b141b1523bccc261f8231 (diff) | |
| download | yosys-82bbd2f0772e62555eb669eb64883d75de4ca29a.tar.gz yosys-82bbd2f0772e62555eb669eb64883d75de4ca29a.tar.bz2 yosys-82bbd2f0772e62555eb669eb64883d75de4ca29a.zip | |
Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012
Diffstat (limited to 'frontends/ast/ast.cc')
| -rw-r--r-- | frontends/ast/ast.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 967111d30..3f704bea4 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -783,6 +783,8 @@ double AstNode::asReal(bool is_signed) double v = 0; for (size_t i = 0; i < val.bits.size(); i++) + // IEEE Std 1800-2012 Par 6.12.2: Individual bits that are x or z in + // the net or the variable shall be treated as zero upon conversion. if (val.bits.at(i) == RTLIL::State::S1) v += exp2(i); if (is_negative) |