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| author | Clifford Wolf <clifford@clifford.at> | 2016-06-19 15:48:40 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-06-19 15:48:40 +0200 |
| commit | 9bca8ccd40d70b6f6ad218cb9b1ae7dd4d3e8e68 (patch) | |
| tree | 74840e34ae02c49884e81916eb81be4fd93c006d /frontends/ast/ast.cc | |
| parent | ca91bccb6b03a0b098f80bf14b55a1444eef73c0 (diff) | |
| parent | a8200a773fb8cf2ce2d8793716b62e01c97dd731 (diff) | |
| download | yosys-9bca8ccd40d70b6f6ad218cb9b1ae7dd4d3e8e68.tar.gz yosys-9bca8ccd40d70b6f6ad218cb9b1ae7dd4d3e8e68.tar.bz2 yosys-9bca8ccd40d70b6f6ad218cb9b1ae7dd4d3e8e68.zip | |
Merge branch 'sv_packages' of https://github.com/rubund/yosys
Diffstat (limited to 'frontends/ast/ast.cc')
| -rw-r--r-- | frontends/ast/ast.cc | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 3ba97ed9b..57de725d8 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -151,6 +151,7 @@ std::string AST::type2str(AstNodeType type) X(AST_POSEDGE) X(AST_NEGEDGE) X(AST_EDGE) + X(AST_PACKAGE) #undef X default: log_abort(); @@ -996,6 +997,14 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump for (auto n : global_decls) (*it)->children.push_back(n->clone()); + for (auto n : design->verilog_packages){ + for (auto o : n->children) { + AstNode *cloned_node = o->clone(); + cloned_node->str = n->str + std::string("::") + cloned_node->str.substr(1); + (*it)->children.push_back(cloned_node); + } + } + if (flag_icells && (*it)->str.substr(0, 2) == "\\$") (*it)->str = (*it)->str.substr(1); @@ -1013,6 +1022,9 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump design->add(process_module(*it, defer)); } + else if ((*it)->type == AST_PACKAGE){ + design->verilog_packages.push_back((*it)->clone()); + } else global_decls.push_back(*it); } |