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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-20 17:24:06 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-20 17:24:06 -0700 |
| commit | 9dc11cd842952deca8e826b662f4565e2b52bd1d (patch) | |
| tree | 6caa919ebcb4618581d8dce4a43f98dbe585bda8 /frontends/ast/ast.h | |
| parent | b25254020c7edc9e4d3fb2a24be5f029a09a1ee0 (diff) | |
| parent | f84a84e3f1a27b361c21fcd30fcf50c1a6586629 (diff) | |
| download | yosys-9dc11cd842952deca8e826b662f4565e2b52bd1d.tar.gz yosys-9dc11cd842952deca8e826b662f4565e2b52bd1d.tar.bz2 yosys-9dc11cd842952deca8e826b662f4565e2b52bd1d.zip | |
Merge remote-tracking branch 'origin/master' into xc7srl
Diffstat (limited to 'frontends/ast/ast.h')
| -rw-r--r-- | frontends/ast/ast.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index ddd59d4be..610e00fbf 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -283,13 +283,13 @@ namespace AST // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil, bool nolatches, bool nomeminit, - bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire); + bool nomem2reg, bool mem2reg, bool lib, bool wb, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire); // parametric modules are supported directly by the AST library // therefore we need our own derivate of RTLIL::Module with overloaded virtual functions struct AstModule : RTLIL::Module { AstNode *ast; - bool nolatches, nomeminit, nomem2reg, mem2reg, lib, noopt, icells, autowire; + bool nolatches, nomeminit, nomem2reg, mem2reg, lib, wb, noopt, icells, autowire; ~AstModule() YS_OVERRIDE; RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail) YS_OVERRIDE; RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, dict<RTLIL::IdString, RTLIL::IdString> modports, bool mayfail) YS_OVERRIDE; |