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| author | Marcin Kościelnicki <mwk@0x04.net> | 2020-02-02 11:26:00 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-02-02 14:34:21 +0100 |
| commit | b44d0e041f09216dd90dccd3f18f146b1dfb7e92 (patch) | |
| tree | 1d15fba3f2ace7f3728a769470f62f64104dc6cc /frontends/ast/ast.h | |
| parent | 00fba627118fb536686b3d30f3b81f71b513cd51 (diff) | |
| download | yosys-b44d0e041f09216dd90dccd3f18f146b1dfb7e92.tar.gz yosys-b44d0e041f09216dd90dccd3f18f146b1dfb7e92.tar.bz2 yosys-b44d0e041f09216dd90dccd3f18f146b1dfb7e92.zip | |
xilinx: use RAM32M/RAM64M for memories with two read ports
This fixes inefficient LUT RAM usage for memories with one write
and two read ports (commonly used as register files).
Diffstat (limited to 'frontends/ast/ast.h')
0 files changed, 0 insertions, 0 deletions