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| author | Clifford Wolf <clifford@clifford.at> | 2018-10-18 10:58:47 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-10-18 10:58:47 +0200 |
| commit | f24bc1ed0a80e48bc23ae68169b6b0bbce5f113c (patch) | |
| tree | 1778829a6932d18730a3a085a80a65205189c7ba /frontends/ast/ast.h | |
| parent | 24a5c6585678f89058382fe2c3f36b821b419e90 (diff) | |
| parent | 736105b0468f9468f00915cad60949535ce5a496 (diff) | |
| download | yosys-f24bc1ed0a80e48bc23ae68169b6b0bbce5f113c.tar.gz yosys-f24bc1ed0a80e48bc23ae68169b6b0bbce5f113c.tar.bz2 yosys-f24bc1ed0a80e48bc23ae68169b6b0bbce5f113c.zip | |
Merge pull request #659 from rubund/sv_interfaces
Support for SystemVerilog interfaces and modports
Diffstat (limited to 'frontends/ast/ast.h')
| -rw-r--r-- | frontends/ast/ast.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 7e97bdb3b..8187b1ac6 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -142,6 +142,11 @@ namespace AST AST_NEGEDGE, AST_EDGE, + AST_INTERFACE, + AST_INTERFACEPORT, + AST_INTERFACEPORTTYPE, + AST_MODPORT, + AST_MODPORTMEMBER, AST_PACKAGE }; @@ -284,6 +289,9 @@ namespace AST bool nolatches, nomeminit, nomem2reg, mem2reg, lib, noopt, icells, autowire; ~AstModule() YS_OVERRIDE; RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail) YS_OVERRIDE; + RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, dict<RTLIL::IdString, RTLIL::IdString> modports, bool mayfail) YS_OVERRIDE; + std::string derive_common(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, AstNode **new_ast_out, bool mayfail); + void reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module *> local_interfaces) YS_OVERRIDE; RTLIL::Module *clone() const YS_OVERRIDE; }; |