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| author | Clifford Wolf <clifford@clifford.at> | 2019-03-02 08:40:54 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-02 08:40:54 -0800 |
| commit | f2f5ecd83468fc94bf1ec8d72734fa531d0b2b32 (patch) | |
| tree | d1a6fee68566d6a560219e2f20e9a4d578704de1 /frontends/ast/ast.h | |
| parent | 67b78ea4fbb8b7d2fc36bb66e4e51e0e5c8d7d9a (diff) | |
| parent | 7cfae2c52fb8e210a68032a109646785e4353dcc (diff) | |
| download | yosys-f2f5ecd83468fc94bf1ec8d72734fa531d0b2b32.tar.gz yosys-f2f5ecd83468fc94bf1ec8d72734fa531d0b2b32.tar.bz2 yosys-f2f5ecd83468fc94bf1ec8d72734fa531d0b2b32.zip | |
Merge pull request #843 from YosysHQ/clifford/mem2regconstidx
Use mem2reg on memories that only have constant-index write ports
Diffstat (limited to 'frontends/ast/ast.h')
| -rw-r--r-- | frontends/ast/ast.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 08f91c9c3..89f7e6e4f 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -214,6 +214,8 @@ namespace AST MEM2REG_FL_SET_ASYNC = 0x00000800, MEM2REG_FL_EQ2 = 0x00001000, MEM2REG_FL_CMPLX_LHS = 0x00002000, + MEM2REG_FL_CONST_LHS = 0x00004000, + MEM2REG_FL_VAR_LHS = 0x00008000, /* proc flags */ MEM2REG_FL_EQ1 = 0x01000000, |