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| author | Clifford Wolf <clifford@clifford.at> | 2018-10-20 23:28:09 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-10-20 23:28:09 +0200 |
| commit | f3de732fb4c85c02b64822c0c557a25b158e80ee (patch) | |
| tree | eb537e2edc2e2eebd2cac62b242501650ea56be3 /frontends/ast/ast.h | |
| parent | 11c8a9eb960fdb0a412fabcfbe787cbf5cc3a67d (diff) | |
| parent | 436e3c0a7cbe5a482e14857e4e5a1d02b3464ae8 (diff) | |
| download | yosys-f3de732fb4c85c02b64822c0c557a25b158e80ee.tar.gz yosys-f3de732fb4c85c02b64822c0c557a25b158e80ee.tar.bz2 yosys-f3de732fb4c85c02b64822c0c557a25b158e80ee.zip | |
Merge pull request #674 from rubund/feature/svinterface_at_top
Support for SystemVerilog interfaces as ports in the top level module + test case
Diffstat (limited to 'frontends/ast/ast.h')
| -rw-r--r-- | frontends/ast/ast.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 8187b1ac6..08f91c9c3 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -308,6 +308,11 @@ namespace AST // call a DPI function AstNode *dpi_call(const std::string &rtype, const std::string &fname, const std::vector<std::string> &argtypes, const std::vector<AstNode*> &args); + + // Helper functions related to handling SystemVerilog interfaces + std::pair<std::string,std::string> split_modport_from_type(std::string name_type); + AstNode * find_modport(AstNode *intf, std::string name); + void explode_interface_port(AstNode *module_ast, RTLIL::Module * intfmodule, std::string intfname, AstNode *modport); } namespace AST_INTERNAL |