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| author | Clifford Wolf <clifford@clifford.at> | 2014-02-17 14:28:52 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-02-17 14:28:52 +0100 |
| commit | 02e6f2c5be8c5514cc8cdb7b3344f6170fb87af9 (patch) | |
| tree | e5adb1a2baa9eba28f7c28bf755d00da266bfe52 /frontends/ast/genrtlil.cc | |
| parent | 0851c2b6ea7044d9bce2014a2be2365a2bf7e1b0 (diff) | |
| download | yosys-02e6f2c5be8c5514cc8cdb7b3344f6170fb87af9.tar.gz yosys-02e6f2c5be8c5514cc8cdb7b3344f6170fb87af9.tar.bz2 yosys-02e6f2c5be8c5514cc8cdb7b3344f6170fb87af9.zip | |
Added Verilog support for "`default_nettype none"
Diffstat (limited to 'frontends/ast/genrtlil.cc')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 12fe23fd8..bc3783bda 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -921,7 +921,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) RTLIL::Wire *wire = new RTLIL::Wire; wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); wire->name = str; - log("Warning: Identifier `%s' is implicitly declared at %s:%d.\n", str.c_str(), filename.c_str(), linenum); + if (flag_autowire) + log("Warning: Identifier `%s' is implicitly declared at %s:%d.\n", str.c_str(), filename.c_str(), linenum); + else + log_error("Identifier `%s' is implicitly declared at %s:%d and `default_nettype is set to none.\n", str.c_str(), filename.c_str(), linenum); current_module->wires[str] = wire; } else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM) { |