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| author | Clifford Wolf <clifford@clifford.at> | 2013-06-13 11:18:45 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-06-13 11:18:45 +0200 |
| commit | 0c6ffc4c656de69c92727580cd4c192211d10e6d (patch) | |
| tree | 9ad133c4d71f687f1046692e1a80481d3d114a89 /frontends/ast/genrtlil.cc | |
| parent | b1d39aa8656f8440eb748fbc7b5673d2129a2308 (diff) | |
| download | yosys-0c6ffc4c656de69c92727580cd4c192211d10e6d.tar.gz yosys-0c6ffc4c656de69c92727580cd4c192211d10e6d.tar.bz2 yosys-0c6ffc4c656de69c92727580cd4c192211d10e6d.zip | |
More fixes for bugs found using xsthammer
Diffstat (limited to 'frontends/ast/genrtlil.cc')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index cb59246c6..aa5a98c41 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -752,7 +752,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint) RTLIL::SigSpec arg = children[0]->genRTLIL(width_hint); is_signed = type == AST_NEG || (type == AST_POS && children[0]->is_signed); int width = type == AST_NEG && arg.width < width_hint ? arg.width+1 : arg.width; - if (width > width_hint && width_hint > 0) + if (width_hint > 0) width = width_hint; return uniop2rtlil(this, type_name, width, arg); } @@ -766,9 +766,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint) RTLIL::SigSpec left = children[0]->genRTLIL(width_hint); RTLIL::SigSpec right = children[1]->genRTLIL(width_hint); int width = std::max(left.width, right.width); - if (width > width_hint && width_hint > 0) - width = width_hint; - if (width < width_hint) + if (width_hint > 0) width = width_hint; return binop2rtlil(this, type_name, width, left, right); } |