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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-02-08 22:12:29 -0800 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-02-08 22:12:29 -0800 |
| commit | 0d7e71f7abd49d1c95f0657993b55bb5f66317a1 (patch) | |
| tree | b2f77c79c6335d9b2b9dde1938f445c48ba00164 /frontends/ast/genrtlil.cc | |
| parent | 0c83a30f950d766ddd09bb744ee93e2433095b5c (diff) | |
| parent | ef4a28e112be10d3d62395f68e53e8b7e42dbf68 (diff) | |
| download | yosys-0d7e71f7abd49d1c95f0657993b55bb5f66317a1.tar.gz yosys-0d7e71f7abd49d1c95f0657993b55bb5f66317a1.tar.bz2 yosys-0d7e71f7abd49d1c95f0657993b55bb5f66317a1.zip | |
Merge https://github.com/cliffordwolf/yosys
Diffstat (limited to 'frontends/ast/genrtlil.cc')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index db8d7409f..bdac4de00 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1336,9 +1336,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // generate $assert cells case AST_ASSERT: case AST_ASSUME: + case AST_COVER: { const char *celltype = "$assert"; if (type == AST_ASSUME) celltype = "$assume"; + if (type == AST_COVER) celltype = "$cover"; log_assert(children.size() == 2); |