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| author | Clifford Wolf <clifford@clifford.at> | 2019-03-07 11:17:32 -0800 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-03-07 11:17:32 -0800 |
| commit | 22ff60850e68b5e98d4693a9a06ec688dac6d5ee (patch) | |
| tree | 682039772eac2e8bdb137ec5722cbdae0dc626a3 /frontends/ast/genrtlil.cc | |
| parent | cda37830b060fd46834d8eb7af1171a1ffaee8ca (diff) | |
| download | yosys-22ff60850e68b5e98d4693a9a06ec688dac6d5ee.tar.gz yosys-22ff60850e68b5e98d4693a9a06ec688dac6d5ee.tar.bz2 yosys-22ff60850e68b5e98d4693a9a06ec688dac6d5ee.zip | |
Add support for SVA labels in read_verilog
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends/ast/genrtlil.cc')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 13383845a..d7da6fb40 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1413,10 +1413,16 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (GetSize(en) != 1) en = current_module->ReduceBool(NEW_ID, en); - std::stringstream sstr; - sstr << celltype << "$" << filename << ":" << linenum << "$" << (autoidx++); + IdString cellname; + if (str.empty()) { + std::stringstream sstr; + sstr << celltype << "$" << filename << ":" << linenum << "$" << (autoidx++); + cellname = sstr.str(); + } else { + cellname = str; + } - RTLIL::Cell *cell = current_module->addCell(sstr.str(), celltype); + RTLIL::Cell *cell = current_module->addCell(cellname, celltype); cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); for (auto &attr : attributes) { |