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| author | tklam <tklam@easylogic.hk> | 2018-10-03 21:17:03 +0800 |
|---|---|---|
| committer | tklam <tklam@easylogic.hk> | 2018-10-03 21:17:03 +0800 |
| commit | 27c46d94e32a45762b3a424d6c7bfcd3ce7a1b12 (patch) | |
| tree | 24b47553fb2aff94f4bd15315f3d43e29db5d30f /frontends/ast/genrtlil.cc | |
| parent | b86eb3deef7d80fc5450379c80047636832ef458 (diff) | |
| parent | 76baae4b946cdeb04026120b495c87a6146358d0 (diff) | |
| download | yosys-27c46d94e32a45762b3a424d6c7bfcd3ce7a1b12.tar.gz yosys-27c46d94e32a45762b3a424d6c7bfcd3ce7a1b12.tar.bz2 yosys-27c46d94e32a45762b3a424d6c7bfcd3ce7a1b12.zip | |
Merge branch 'master' of https://github.com/YosysHQ/yosys
Diffstat (limited to 'frontends/ast/genrtlil.cc')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 0f7e910f3..c9345ff08 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -985,7 +985,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) use_const_chunk: if (children.size() != 0) { - log_assert(children[0]->type == AST_RANGE); + if (children[0]->type != AST_RANGE) + log_file_error(filename, linenum, "Single range expected.\n"); int source_width = id2ast->range_left - id2ast->range_right + 1; int source_offset = id2ast->range_right; if (!children[0]->range_valid) { |