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| author | Clifford Wolf <clifford@clifford.at> | 2019-05-27 13:25:52 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-05-27 13:25:52 +0200 |
| commit | 40a070e269ac5dbc88d2f81a4d9b340ecb524009 (patch) | |
| tree | fff2c69cd5f045777b43a93469793fd7375f081d /frontends/ast/genrtlil.cc | |
| parent | 2a9c68e2d6e0d58ac9e1ef8e8eb4c21eb979b380 (diff) | |
| parent | 34417ce55f1b1d71ac11dfdfecfffc7a3340b6cb (diff) | |
| download | yosys-40a070e269ac5dbc88d2f81a4d9b340ecb524009.tar.gz yosys-40a070e269ac5dbc88d2f81a4d9b340ecb524009.tar.bz2 yosys-40a070e269ac5dbc88d2f81a4d9b340ecb524009.zip | |
Merge pull request #1043 from mmicko/unsized_constant
Added support for unsized constants, fixes #1022
Diffstat (limited to 'frontends/ast/genrtlil.cc')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 379fed641..d9dfc17cc 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -963,8 +963,13 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) detectSignWidth(width_hint, sign_hint); is_signed = sign_hint; - if (type == AST_CONSTANT) - return RTLIL::SigSpec(bitsAsConst()); + if (type == AST_CONSTANT) { + if (is_unsized) { + return RTLIL::SigSpec(bitsAsUnsizedConst(width_hint)); + } else { + return RTLIL::SigSpec(bitsAsConst()); + } + } RTLIL::SigSpec sig = realAsConst(width_hint); log_file_warning(filename, linenum, "converting real value %e to binary %s.\n", realvalue, log_signal(sig)); |