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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-16 12:23:47 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-16 12:49:50 +0200 |
| commit | 543551b80a257ce0d55ce2d97fed165da7750360 (patch) | |
| tree | 13dadaf5c36fc6af78a45e5c07a584ae1adc281c /frontends/ast/genrtlil.cc | |
| parent | 765f172211c8d7d8f14b6010193d8b53f5ec5e8f (diff) | |
| download | yosys-543551b80a257ce0d55ce2d97fed165da7750360.tar.gz yosys-543551b80a257ce0d55ce2d97fed165da7750360.tar.bz2 yosys-543551b80a257ce0d55ce2d97fed165da7750360.zip | |
changes in verilog frontend for new $mem/$memwr WR_EN interface
Diffstat (limited to 'frontends/ast/genrtlil.cc')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 787f4d2d8..a2fdcf8b1 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1287,9 +1287,6 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) cell->connections["\\DATA"] = children[1]->genWidthRTLIL(current_module->memories[str]->width); cell->connections["\\EN"] = children[2]->genRTLIL(); - if (cell->connections["\\EN"].width > 1) - cell->connections["\\EN"] = uniop2rtlil(this, "$reduce_bool", 1, cell->connections["\\EN"], false); - cell->parameters["\\MEMID"] = RTLIL::Const(str); cell->parameters["\\ABITS"] = RTLIL::Const(addr_bits); cell->parameters["\\WIDTH"] = RTLIL::Const(current_module->memories[str]->width); |