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| author | Clifford Wolf <clifford@clifford.at> | 2013-03-31 11:17:56 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2013-03-31 11:17:56 +0200 |
| commit | 5640b7d6078a681e33e85f06920394204f41c875 (patch) | |
| tree | 96ebae5ed0626ae5238fe8b794e50e0cb9d87e7c /frontends/ast/genrtlil.cc | |
| parent | 04843bdcbeb62a202a6372ea5464de8c7ea66820 (diff) | |
| download | yosys-5640b7d6078a681e33e85f06920394204f41c875.tar.gz yosys-5640b7d6078a681e33e85f06920394204f41c875.tar.bz2 yosys-5640b7d6078a681e33e85f06920394204f41c875.zip | |
Added test cases from 2012 paper on comparison of foss verilog synthesis tools
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