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| author | Clifford Wolf <clifford@clifford.at> | 2013-07-04 14:12:33 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-07-04 14:12:33 +0200 |
| commit | 56432a920f9c2189ead2f724f18cde20aad7bf99 (patch) | |
| tree | 37c83554247ef98dfba58409993b8f1d2379aa09 /frontends/ast/genrtlil.cc | |
| parent | 3b294b391202bdac25c822cc06d7572249b38949 (diff) | |
| download | yosys-56432a920f9c2189ead2f724f18cde20aad7bf99.tar.gz yosys-56432a920f9c2189ead2f724f18cde20aad7bf99.tar.bz2 yosys-56432a920f9c2189ead2f724f18cde20aad7bf99.zip | |
Added defparam support to Verilog/AST frontend
Diffstat (limited to 'frontends/ast/genrtlil.cc')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index aa5a98c41..03bb8a430 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -531,6 +531,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint) case AST_AUTOWIRE: case AST_PARAMETER: case AST_LOCALPARAM: + case AST_DEFPARAM: case AST_GENVAR: case AST_GENFOR: case AST_GENBLOCK: |