diff options
| author | Clifford Wolf <clifford@clifford.at> | 2013-11-24 17:17:21 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-24 17:17:21 +0100 |
| commit | 609caa23b5e12547c043dc4a1827d1a531af1992 (patch) | |
| tree | 297e7d5b77b28eebccc3bd8e7af318f174165744 /frontends/ast/genrtlil.cc | |
| parent | 1e6836933d8b74d391f816ccdcf71c972f8b1db1 (diff) | |
| download | yosys-609caa23b5e12547c043dc4a1827d1a531af1992.tar.gz yosys-609caa23b5e12547c043dc4a1827d1a531af1992.tar.bz2 yosys-609caa23b5e12547c043dc4a1827d1a531af1992.zip | |
Implemented correct handling of signed module parameters
Diffstat (limited to 'frontends/ast/genrtlil.cc')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index e634a27a9..177c1ec59 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1309,9 +1309,13 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (child->str.size() == 0) { char buf[100]; snprintf(buf, 100, "$%d", ++para_counter); + if (child->children[0]->is_signed) + cell->signed_parameters.insert(buf); cell->parameters[buf].str = child->children[0]->str; cell->parameters[buf].bits = child->children[0]->bits; } else { + if (child->children[0]->is_signed) + cell->signed_parameters.insert(child->str); cell->parameters[child->str].str = child->children[0]->str; cell->parameters[child->str].bits = child->children[0]->bits; } |