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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 11:17:19 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 11:17:19 -0700 |
| commit | 63eb5cace980cd34e59065e577c04abaad239ddf (patch) | |
| tree | be065a052bda42a4654e4a1483f9fcde0beacef9 /frontends/ast/genrtlil.cc | |
| parent | 776d7cea6ad42a58f47cdcb7a71a801e1ea1055f (diff) | |
| parent | c4ea6fff65d6b2e69a31649af7e10b129c6ae0f5 (diff) | |
| download | yosys-63eb5cace980cd34e59065e577c04abaad239ddf.tar.gz yosys-63eb5cace980cd34e59065e577c04abaad239ddf.tar.bz2 yosys-63eb5cace980cd34e59065e577c04abaad239ddf.zip | |
Merge branch 'master' into eddie/muxpack
Diffstat (limited to 'frontends/ast/genrtlil.cc')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 32ed401eb..079fc11e5 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -853,7 +853,6 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) case AST_FUNCTION: case AST_DPI_FUNCTION: case AST_AUTOWIRE: - case AST_LOCALPARAM: case AST_DEFPARAM: case AST_GENVAR: case AST_GENFOR: @@ -895,6 +894,26 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // remember the parameter, needed for example in techmap case AST_PARAMETER: current_module->avail_parameters.insert(str); + /* fall through */ + case AST_LOCALPARAM: + if (flag_pwires) + { + if (GetSize(children) < 1 || children[0]->type != AST_CONSTANT) + log_file_error(filename, linenum, "Parameter `%s' with non-constant value!\n", str.c_str()); + + RTLIL::Const val = children[0]->bitsAsConst(); + RTLIL::Wire *wire = current_module->addWire(str, GetSize(val)); + current_module->connect(wire, val); + + wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); + wire->attributes[type == AST_PARAMETER ? "\\parameter" : "\\localparam"] = 1; + + for (auto &attr : attributes) { + if (attr.second->type != AST_CONSTANT) + log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); + wire->attributes[attr.first] = attr.second->asAttrConst(); + } + } break; // create an RTLIL::Wire for an AST_WIRE node |