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authorClifford Wolf <clifford@clifford.at>2016-06-19 15:48:40 +0200
committerClifford Wolf <clifford@clifford.at>2016-06-19 15:48:40 +0200
commit9bca8ccd40d70b6f6ad218cb9b1ae7dd4d3e8e68 (patch)
tree74840e34ae02c49884e81916eb81be4fd93c006d /frontends/ast/genrtlil.cc
parentca91bccb6b03a0b098f80bf14b55a1444eef73c0 (diff)
parenta8200a773fb8cf2ce2d8793716b62e01c97dd731 (diff)
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Merge branch 'sv_packages' of https://github.com/rubund/yosys
Diffstat (limited to 'frontends/ast/genrtlil.cc')
-rw-r--r--frontends/ast/genrtlil.cc1
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 0e5029eb4..3e359170b 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -806,6 +806,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
case AST_GENBLOCK:
case AST_GENIF:
case AST_GENCASE:
+ case AST_PACKAGE:
break;
// remember the parameter, needed for example in techmap